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Adding in curl and openssl repos

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Laan Tungir
2025-08-14 12:09:30 -04:00
parent af2117b574
commit 0ace93e303
21174 changed files with 3607720 additions and 2 deletions
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280
openssl-3.4.2/crypto/sm3/asm/sm3-armv8.pl Normal file
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#! /usr/bin/env perl
# Copyright 2021-2025 The OpenSSL Project Authors. All Rights Reserved.
#
# Licensed under the Apache License 2.0 (the "License"). You may not use
# this file except in compliance with the License. You can obtain a copy
# in the file LICENSE in the source distribution or at
# https://www.openssl.org/source/license.html
#
# This module implements support for Armv8 SM3 instructions
# $output is the last argument if it looks like a file (it has an extension)
# $flavour is the first argument if it doesn't look like a file
$output = $#ARGV >= 0 && $ARGV[$#ARGV] =~ m|\.\w+$| ? pop : undef;
$flavour = $#ARGV >= 0 && $ARGV[0] !~ m|\.| ? shift : undef;
$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or
( $xlate="${dir}../../perlasm/arm-xlate.pl" and -f $xlate) or
die "can't locate arm-xlate.pl";
open OUT,"| \"$^X\" $xlate $flavour \"$output\""
or die "can't call $xlate: $!";
*STDOUT=*OUT;
# Message expanding:
# Wj <- P1(W[j-16]^W[j-9]^(W[j-3]<<<15))^(W[j-13]<<<7)^W[j-6]
# Input: s0, s1, s2, s3
# s0 = w0 | w1 | w2 | w3
# s1 = w4 | w5 | w6 | w7
# s2 = w8 | w9 | w10 | w11
# s3 = w12 | w13 | w14 | w15
# Output: s4
sub msg_exp () {
my $s0 = shift;
my $s1 = shift;
my $s2 = shift;
my $s3 = shift;
my $s4 = shift;
my $vtmp1 = shift;
my $vtmp2 = shift;
$code.=<<___;
// s4 = w7 | w8 | w9 | w10
ext $s4.16b, $s1.16b, $s2.16b, #12
// vtmp1 = w3 | w4 | w5 | w6
ext $vtmp1.16b, $s0.16b, $s1.16b, #12
// vtmp2 = w10 | w11 | w12 | w13
ext $vtmp2.16b, $s2.16b, $s3.16b, #8
sm3partw1 $s4.4s, $s0.4s, $s3.4s
sm3partw2 $s4.4s, $vtmp2.4s, $vtmp1.4s
___
}
# A round of compresson function
# Input:
# ab - choose instruction among sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b
# vstate0 - vstate1, store digest status(A - H)
# vconst0 - vconst1, interleaved used to store Tj <<< j
# vtmp - temporary register
# vw - for sm3tt1ab, vw = s0 eor s1
# s0 - for sm3tt2ab, just be s0
# i, choose wj' or wj from vw
sub round () {
my $ab = shift;
my $vstate0 = shift;
my $vstate1 = shift;
my $vconst0 = shift;
my $vconst1 = shift;
my $vtmp = shift;
my $vw = shift;
my $s0 = shift;
my $i = shift;
$code.=<<___;
sm3ss1 $vtmp.4s, $vstate0.4s, $vconst0.4s, $vstate1.4s
shl $vconst1.4s, $vconst0.4s, #1
sri $vconst1.4s, $vconst0.4s, #31
sm3tt1$ab $vstate0.4s, $vtmp.4s, $vw.4s[$i]
sm3tt2$ab $vstate1.4s, $vtmp.4s, $s0.4s[$i]
___
}
sub qround () {
my $ab = shift;
my $vstate0 = shift;
my $vstate1 = shift;
my $vconst0 = shift;
my $vconst1 = shift;
my $vtmp1 = shift;
my $vtmp2 = shift;
my $s0 = shift;
my $s1 = shift;
my $s2 = shift;
my $s3 = shift;
my $s4 = shift;
if($s4) {
&msg_exp($s0, $s1, $s2, $s3, $s4, $vtmp1, $vtmp2);
}
$code.=<<___;
eor $vtmp1.16b, $s0.16b, $s1.16b
___
&round($ab, $vstate0, $vstate1, $vconst0, $vconst1, $vtmp2,
$vtmp1, $s0, 0);
&round($ab, $vstate0, $vstate1, $vconst1, $vconst0, $vtmp2,
$vtmp1, $s0, 1);
&round($ab, $vstate0, $vstate1, $vconst0, $vconst1, $vtmp2,
$vtmp1, $s0, 2);
&round($ab, $vstate0, $vstate1, $vconst1, $vconst0, $vtmp2,
$vtmp1, $s0, 3);
}
$code=<<___;
#include "arm_arch.h"
.text
___
{{{
my ($pstate,$pdata,$num)=("x0","x1","w2");
my ($state1,$state2)=("v5","v6");
my ($sconst1, $sconst2)=("s16","s17");
my ($vconst1, $vconst2)=("v16","v17");
my ($s0,$s1,$s2,$s3,$s4)=map("v$_",(0..4));
my ($bkstate1,$bkstate2)=("v18","v19");
my ($vconst_tmp1,$vconst_tmp2)=("v20","v21");
my ($vtmp1,$vtmp2)=("v22","v23");
my $constaddr="x8";
# void ossl_hwsm3_block_data_order(SM3_CTX *c, const void *p, size_t num)
$code.=<<___;
.globl ossl_hwsm3_block_data_order
.type ossl_hwsm3_block_data_order,%function
.align 5
ossl_hwsm3_block_data_order:
AARCH64_VALID_CALL_TARGET
// load state
ld1 {$state1.4s-$state2.4s}, [$pstate]
rev64 $state1.4s, $state1.4s
rev64 $state2.4s, $state2.4s
ext $state1.16b, $state1.16b, $state1.16b, #8
ext $state2.16b, $state2.16b, $state2.16b, #8
adr $constaddr, .Tj
ldp $sconst1, $sconst2, [$constaddr]
.Loop:
// load input
ld1 {$s0.4s-$s3.4s}, [$pdata], #64
sub $num, $num, #1
mov $bkstate1.16b, $state1.16b
mov $bkstate2.16b, $state2.16b
#ifndef __AARCH64EB__
rev32 $s0.16b, $s0.16b
rev32 $s1.16b, $s1.16b
rev32 $s2.16b, $s2.16b
rev32 $s3.16b, $s3.16b
#endif
ext $vconst_tmp1.16b, $vconst1.16b, $vconst1.16b, #4
___
&qround("a",$state1,$state2,$vconst_tmp1,$vconst_tmp2,$vtmp1,$vtmp2,
$s0,$s1,$s2,$s3,$s4);
&qround("a",$state1,$state2,$vconst_tmp1,$vconst_tmp2,$vtmp1,$vtmp2,
$s1,$s2,$s3,$s4,$s0);
&qround("a",$state1,$state2,$vconst_tmp1,$vconst_tmp2,$vtmp1,$vtmp2,
$s2,$s3,$s4,$s0,$s1);
&qround("a",$state1,$state2,$vconst_tmp1,$vconst_tmp2,$vtmp1,$vtmp2,
$s3,$s4,$s0,$s1,$s2);
$code.=<<___;
ext $vconst_tmp1.16b, $vconst2.16b, $vconst2.16b, #4
___
&qround("b",$state1,$state2,$vconst_tmp1,$vconst_tmp2,$vtmp1,$vtmp2,
$s4,$s0,$s1,$s2,$s3);
&qround("b",$state1,$state2,$vconst_tmp1,$vconst_tmp2,$vtmp1,$vtmp2,
$s0,$s1,$s2,$s3,$s4);
&qround("b",$state1,$state2,$vconst_tmp1,$vconst_tmp2,$vtmp1,$vtmp2,
$s1,$s2,$s3,$s4,$s0);
&qround("b",$state1,$state2,$vconst_tmp1,$vconst_tmp2,$vtmp1,$vtmp2,
$s2,$s3,$s4,$s0,$s1);
&qround("b",$state1,$state2,$vconst_tmp1,$vconst_tmp2,$vtmp1,$vtmp2,
$s3,$s4,$s0,$s1,$s2);
&qround("b",$state1,$state2,$vconst_tmp1,$vconst_tmp2,$vtmp1,$vtmp2,
$s4,$s0,$s1,$s2,$s3);
&qround("b",$state1,$state2,$vconst_tmp1,$vconst_tmp2,$vtmp1,$vtmp2,
$s0,$s1,$s2,$s3,$s4);
&qround("b",$state1,$state2,$vconst_tmp1,$vconst_tmp2,$vtmp1,$vtmp2,
$s1,$s2,$s3,$s4,$s0);
&qround("b",$state1,$state2,$vconst_tmp1,$vconst_tmp2,$vtmp1,$vtmp2,
$s2,$s3,$s4,$s0,$s1);
&qround("b",$state1,$state2,$vconst_tmp1,$vconst_tmp2,$vtmp1,$vtmp2,
$s3,$s4);
&qround("b",$state1,$state2,$vconst_tmp1,$vconst_tmp2,$vtmp1,$vtmp2,
$s4,$s0);
&qround("b",$state1,$state2,$vconst_tmp1,$vconst_tmp2,$vtmp1,$vtmp2,
$s0,$s1);
$code.=<<___;
eor $state1.16b, $state1.16b, $bkstate1.16b
eor $state2.16b, $state2.16b, $bkstate2.16b
// any remained blocks?
cbnz $num, .Loop
// save state
rev64 $state1.4s, $state1.4s
rev64 $state2.4s, $state2.4s
ext $state1.16b, $state1.16b, $state1.16b, #8
ext $state2.16b, $state2.16b, $state2.16b, #8
st1 {$state1.4s-$state2.4s}, [$pstate]
ret
.size ossl_hwsm3_block_data_order,.-ossl_hwsm3_block_data_order
.align 3
.Tj:
.word 0x79cc4519, 0x9d8a7a87
___
}}}
#########################################
my %sm3partopcode = (
"sm3partw1" => 0xce60C000,
"sm3partw2" => 0xce60C400);
my %sm3ss1opcode = (
"sm3ss1" => 0xce400000);
my %sm3ttopcode = (
"sm3tt1a" => 0xce408000,
"sm3tt1b" => 0xce408400,
"sm3tt2a" => 0xce408800,
"sm3tt2b" => 0xce408C00);
sub unsm3part {
my ($mnemonic,$arg)=@_;
$arg=~ m/[qv](\d+)[^,]*,\s*[qv](\d+)[^,]*,\s*[qv](\d+)/o
&&
sprintf ".inst\t0x%08x\t//%s %s",
$sm3partopcode{$mnemonic}|$1|($2<<5)|($3<<16),
$mnemonic,$arg;
}
sub unsm3ss1 {
my ($mnemonic,$arg)=@_;
$arg=~ m/[qv](\d+)[^,]*,\s*[qv](\d+)[^,]*,\s*[qv](\d+)[^,]*,\s*[qv](\d+)/o
&&
sprintf ".inst\t0x%08x\t//%s %s",
$sm3ss1opcode{$mnemonic}|$1|($2<<5)|($3<<16)|($4<<10),
$mnemonic,$arg;
}
sub unsm3tt {
my ($mnemonic,$arg)=@_;
$arg=~ m/[qv](\d+)[^,]*,\s*[qv](\d+)[^,]*,\s*[qv](\d+)[^,]*\[([0-3])\]/o
&&
sprintf ".inst\t0x%08x\t//%s %s",
$sm3ttopcode{$mnemonic}|$1|($2<<5)|($3<<16)|($4<<12),
$mnemonic,$arg;
}
open SELF,$0;
while(<SELF>) {
next if (/^#!/);
last if (!s/^#/\/\// and !/^$/);
print;
}
close SELF;
foreach(split("\n",$code)) {
s/\`([^\`]*)\`/eval($1)/ge;
s/\b(sm3partw[1-2])\s+([qv].*)/unsm3part($1,$2)/ge;
s/\b(sm3ss1)\s+([qv].*)/unsm3ss1($1,$2)/ge;
s/\b(sm3tt[1-2][a-b])\s+([qv].*)/unsm3tt($1,$2)/ge;
print $_,"\n";
}
close STDOUT or die "error closing STDOUT: $!";

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openssl-3.4.2/crypto/sm3/asm/sm3-riscv64-zvksh.pl Executable file
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#! /usr/bin/env perl
# This file is dual-licensed, meaning that you can use it under your
# choice of either of the following two licenses:
#
# Copyright 2023 The OpenSSL Project Authors. All Rights Reserved.
#
# Licensed under the Apache License 2.0 (the "License"). You can obtain
# a copy in the file LICENSE in the source distribution or at
# https://www.openssl.org/source/license.html
#
# or
#
# Copyright (c) 2023, Christoph Müllner <christoph.muellner@vrull.eu>
# Copyright (c) 2023, Jerry Shih <jerry.shih@sifive.com>
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
# The generated code of this file depends on the following RISC-V extensions:
# - RV64I
# - RISC-V Vector ('V') with VLEN >= 128
# - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb')
# - RISC-V Vector SM3 Secure Hash extension ('Zvksh')
use strict;
use warnings;
use FindBin qw($Bin);
use lib "$Bin";
use lib "$Bin/../../perlasm";
use riscv;
# $output is the last argument if it looks like a file (it has an extension)
# $flavour is the first argument if it doesn't look like a file
my $output = $#ARGV >= 0 && $ARGV[$#ARGV] =~ m|\.\w+$| ? pop : undef;
my $flavour = $#ARGV >= 0 && $ARGV[0] !~ m|\.| ? shift : undef;
$output and open STDOUT,">$output";
my $code=<<___;
.text
___
################################################################################
# ossl_hwsm3_block_data_order_zvksh(SM3_CTX *c, const void *p, size_t num);
{
my ($CTX, $INPUT, $NUM) = ("a0", "a1", "a2");
my ($V0, $V1, $V2, $V3, $V4, $V5, $V6, $V7,
$V8, $V9, $V10, $V11, $V12, $V13, $V14, $V15,
$V16, $V17, $V18, $V19, $V20, $V21, $V22, $V23,
$V24, $V25, $V26, $V27, $V28, $V29, $V30, $V31,
) = map("v$_",(0..31));
$code .= <<___;
.text
.p2align 3
.globl ossl_hwsm3_block_data_order_zvksh
.type ossl_hwsm3_block_data_order_zvksh,\@function
ossl_hwsm3_block_data_order_zvksh:
@{[vsetivli "zero", 8, "e32", "m2", "ta", "ma"]}
# Load initial state of hash context (c->A-H).
@{[vle32_v $V0, $CTX]}
@{[vrev8_v $V0, $V0]}
L_sm3_loop:
# Copy the previous state to v2.
# It will be XOR'ed with the current state at the end of the round.
@{[vmv_v_v $V2, $V0]}
# Load the 64B block in 2x32B chunks.
@{[vle32_v $V6, $INPUT]} # v6 := {w7, ..., w0}
addi $INPUT, $INPUT, 32
@{[vle32_v $V8, $INPUT]} # v8 := {w15, ..., w8}
addi $INPUT, $INPUT, 32
addi $NUM, $NUM, -1
# As vsm3c consumes only w0, w1, w4, w5 we need to slide the input
# 2 elements down so we process elements w2, w3, w6, w7
# This will be repeated for each odd round.
@{[vslidedown_vi $V4, $V6, 2]} # v4 := {X, X, w7, ..., w2}
@{[vsm3c_vi $V0, $V6, 0]}
@{[vsm3c_vi $V0, $V4, 1]}
# Prepare a vector with {w11, ..., w4}
@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, X, X, w7, ..., w4}
@{[vslideup_vi $V4, $V8, 4]} # v4 := {w11, w10, w9, w8, w7, w6, w5, w4}
@{[vsm3c_vi $V0, $V4, 2]}
@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, w11, w10, w9, w8, w7, w6}
@{[vsm3c_vi $V0, $V4, 3]}
@{[vsm3c_vi $V0, $V8, 4]}
@{[vslidedown_vi $V4, $V8, 2]} # v4 := {X, X, w15, w14, w13, w12, w11, w10}
@{[vsm3c_vi $V0, $V4, 5]}
@{[vsm3me_vv $V6, $V8, $V6]} # v6 := {w23, w22, w21, w20, w19, w18, w17, w16}
# Prepare a register with {w19, w18, w17, w16, w15, w14, w13, w12}
@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, X, X, w15, w14, w13, w12}
@{[vslideup_vi $V4, $V6, 4]} # v4 := {w19, w18, w17, w16, w15, w14, w13, w12}
@{[vsm3c_vi $V0, $V4, 6]}
@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, w19, w18, w17, w16, w15, w14}
@{[vsm3c_vi $V0, $V4, 7]}
@{[vsm3c_vi $V0, $V6, 8]}
@{[vslidedown_vi $V4, $V6, 2]} # v4 := {X, X, w23, w22, w21, w20, w19, w18}
@{[vsm3c_vi $V0, $V4, 9]}
@{[vsm3me_vv $V8, $V6, $V8]} # v8 := {w31, w30, w29, w28, w27, w26, w25, w24}
# Prepare a register with {w27, w26, w25, w24, w23, w22, w21, w20}
@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, X, X, w23, w22, w21, w20}
@{[vslideup_vi $V4, $V8, 4]} # v4 := {w27, w26, w25, w24, w23, w22, w21, w20}
@{[vsm3c_vi $V0, $V4, 10]}
@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, w27, w26, w25, w24, w23, w22}
@{[vsm3c_vi $V0, $V4, 11]}
@{[vsm3c_vi $V0, $V8, 12]}
@{[vslidedown_vi $V4, $V8, 2]} # v4 := {x, X, w31, w30, w29, w28, w27, w26}
@{[vsm3c_vi $V0, $V4, 13]}
@{[vsm3me_vv $V6, $V8, $V6]} # v6 := {w32, w33, w34, w35, w36, w37, w38, w39}
# Prepare a register with {w35, w34, w33, w32, w31, w30, w29, w28}
@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, X, X, w31, w30, w29, w28}
@{[vslideup_vi $V4, $V6, 4]} # v4 := {w35, w34, w33, w32, w31, w30, w29, w28}
@{[vsm3c_vi $V0, $V4, 14]}
@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, w35, w34, w33, w32, w31, w30}
@{[vsm3c_vi $V0, $V4, 15]}
@{[vsm3c_vi $V0, $V6, 16]}
@{[vslidedown_vi $V4, $V6, 2]} # v4 := {X, X, w39, w38, w37, w36, w35, w34}
@{[vsm3c_vi $V0, $V4, 17]}
@{[vsm3me_vv $V8, $V6, $V8]} # v8 := {w47, w46, w45, w44, w43, w42, w41, w40}
# Prepare a register with {w43, w42, w41, w40, w39, w38, w37, w36}
@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, X, X, w39, w38, w37, w36}
@{[vslideup_vi $V4, $V8, 4]} # v4 := {w43, w42, w41, w40, w39, w38, w37, w36}
@{[vsm3c_vi $V0, $V4, 18]}
@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, w43, w42, w41, w40, w39, w38}
@{[vsm3c_vi $V0, $V4, 19]}
@{[vsm3c_vi $V0, $V8, 20]}
@{[vslidedown_vi $V4, $V8, 2]} # v4 := {X, X, w47, w46, w45, w44, w43, w42}
@{[vsm3c_vi $V0, $V4, 21]}
@{[vsm3me_vv $V6, $V8, $V6]} # v6 := {w55, w54, w53, w52, w51, w50, w49, w48}
# Prepare a register with {w51, w50, w49, w48, w47, w46, w45, w44}
@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, X, X, w47, w46, w45, w44}
@{[vslideup_vi $V4, $V6, 4]} # v4 := {w51, w50, w49, w48, w47, w46, w45, w44}
@{[vsm3c_vi $V0, $V4, 22]}
@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, w51, w50, w49, w48, w47, w46}
@{[vsm3c_vi $V0, $V4, 23]}
@{[vsm3c_vi $V0, $V6, 24]}
@{[vslidedown_vi $V4, $V6, 2]} # v4 := {X, X, w55, w54, w53, w52, w51, w50}
@{[vsm3c_vi $V0, $V4, 25]}
@{[vsm3me_vv $V8, $V6, $V8]} # v8 := {w63, w62, w61, w60, w59, w58, w57, w56}
# Prepare a register with {w59, w58, w57, w56, w55, w54, w53, w52}
@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, X, X, w55, w54, w53, w52}
@{[vslideup_vi $V4, $V8, 4]} # v4 := {w59, w58, w57, w56, w55, w54, w53, w52}
@{[vsm3c_vi $V0, $V4, 26]}
@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, w59, w58, w57, w56, w55, w54}
@{[vsm3c_vi $V0, $V4, 27]}
@{[vsm3c_vi $V0, $V8, 28]}
@{[vslidedown_vi $V4, $V8, 2]} # v4 := {X, X, w63, w62, w61, w60, w59, w58}
@{[vsm3c_vi $V0, $V4, 29]}
@{[vsm3me_vv $V6, $V8, $V6]} # v6 := {w71, w70, w69, w68, w67, w66, w65, w64}
# Prepare a register with {w67, w66, w65, w64, w63, w62, w61, w60}
@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, X, X, w63, w62, w61, w60}
@{[vslideup_vi $V4, $V6, 4]} # v4 := {w67, w66, w65, w64, w63, w62, w61, w60}
@{[vsm3c_vi $V0, $V4, 30]}
@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, w67, w66, w65, w64, w63, w62}
@{[vsm3c_vi $V0, $V4, 31]}
# XOR in the previous state.
@{[vxor_vv $V0, $V0, $V2]}
bnez $NUM, L_sm3_loop # Check if there are any more block to process
L_sm3_end:
@{[vrev8_v $V0, $V0]}
@{[vse32_v $V0, $CTX]}
ret
.size ossl_hwsm3_block_data_order_zvksh,.-ossl_hwsm3_block_data_order_zvksh
___
}
print $code;
close STDOUT or die "error closing STDOUT: $!";

27
openssl-3.4.2/crypto/sm3/build.info Normal file
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@@ -0,0 +1,27 @@
LIBS=../../libcrypto
IF[{- !$disabled{sm3} -}]
IF[{- !$disabled{asm} -}]
$SM3ASM_aarch64=sm3-armv8.S
$SM3DEF_aarch64=OPENSSL_SM3_ASM
$SM3ASM_riscv64=sm3_riscv.c sm3-riscv64-zvksh.S
$SM3DEF_riscv64=OPENSSL_SM3_ASM
# Now that we have defined all the arch specific variables, use the
# appropriate ones, and define the appropriate macros
IF[$SM3ASM_{- $target{asm_arch} -}]
$SM3ASM=$SM3ASM_{- $target{asm_arch} -}
$SM3DEF=$SM3DEF_{- $target{asm_arch} -}
ENDIF
ENDIF
SOURCE[../../libcrypto]=sm3.c legacy_sm3.c $SM3ASM
DEFINE[../../libcrypto]=$SM3DEF
GENERATE[sm3-armv8.S]=asm/sm3-armv8.pl
INCLUDE[sm3-armv8.o]=..
GENERATE[sm3-riscv64-zvksh.S]=asm/sm3-riscv64-zvksh.pl
ENDIF

31
openssl-3.4.2/crypto/sm3/legacy_sm3.c Normal file
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@@ -0,0 +1,31 @@
/*
* Copyright 2017-2021 The OpenSSL Project Authors. All Rights Reserved.
* Copyright 2017 Ribose Inc. All Rights Reserved.
*
* Licensed under the Apache License 2.0 (the "License"). You may not use
* this file except in compliance with the License. You can obtain a copy
* in the file LICENSE in the source distribution or at
* https://www.openssl.org/source/license.html
*/
#include "crypto/evp.h"
#include "../evp/legacy_meth.h"
#include "internal/sm3.h"
IMPLEMENT_LEGACY_EVP_MD_METH_LC(sm3_int, ossl_sm3)
static const EVP_MD sm3_md = {
NID_sm3,
NID_sm3WithRSAEncryption,
SM3_DIGEST_LENGTH,
0,
EVP_ORIG_GLOBAL,
LEGACY_EVP_MD_METH_TABLE(sm3_int_init, sm3_int_update, sm3_int_final, NULL,
SM3_CBLOCK),
};
const EVP_MD *EVP_sm3(void)
{
return &sm3_md;
}

17
openssl-3.4.2/crypto/sm3/libcrypto-lib-legacy_sm3.d Normal file
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@@ -0,0 +1,17 @@
crypto/sm3/libcrypto-lib-legacy_sm3.o: crypto/sm3/legacy_sm3.c \
include/crypto/evp.h include/openssl/evp.h include/openssl/macros.h \
include/openssl/opensslconf.h include/openssl/configuration.h \
include/openssl/opensslv.h include/openssl/types.h \
include/openssl/e_os2.h include/openssl/safestack.h \
include/openssl/stack.h include/openssl/core.h \
include/openssl/core_dispatch.h include/openssl/indicator.h \
include/openssl/params.h include/openssl/bn.h include/openssl/crypto.h \
include/openssl/cryptoerr.h include/openssl/symhacks.h \
include/openssl/cryptoerr_legacy.h include/openssl/bnerr.h \
include/openssl/bio.h include/openssl/bioerr.h include/openssl/evperr.h \
include/openssl/objects.h include/openssl/obj_mac.h \
include/openssl/asn1.h include/openssl/asn1err.h \
include/openssl/objectserr.h include/internal/refcount.h \
include/openssl/trace.h include/openssl/err.h include/openssl/lhash.h \
include/crypto/ecx.h include/crypto/types.h \
crypto/sm3/../evp/legacy_meth.h include/internal/sm3.h

9
openssl-3.4.2/crypto/sm3/libcrypto-lib-sm3.d Normal file
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@@ -0,0 +1,9 @@
crypto/sm3/libcrypto-lib-sm3.o: crypto/sm3/sm3.c include/openssl/e_os2.h \
include/openssl/macros.h include/openssl/opensslconf.h \
include/openssl/configuration.h include/openssl/opensslv.h \
crypto/sm3/sm3_local.h include/internal/sm3.h \
include/crypto/md32_common.h include/openssl/crypto.h \
include/openssl/safestack.h include/openssl/stack.h \
include/openssl/types.h include/openssl/cryptoerr.h \
include/openssl/symhacks.h include/openssl/cryptoerr_legacy.h \
include/openssl/core.h

195
openssl-3.4.2/crypto/sm3/sm3.c Normal file
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@@ -0,0 +1,195 @@
/*
* Copyright 2017-2021 The OpenSSL Project Authors. All Rights Reserved.
* Copyright 2017 Ribose Inc. All Rights Reserved.
* Ported from Ribose contributions from Botan.
*
* Licensed under the Apache License 2.0 (the "License"). You may not use
* this file except in compliance with the License. You can obtain a copy
* in the file LICENSE in the source distribution or at
* https://www.openssl.org/source/license.html
*/
#include <openssl/e_os2.h>
#include "sm3_local.h"
int ossl_sm3_init(SM3_CTX *c)
{
memset(c, 0, sizeof(*c));
c->A = SM3_A;
c->B = SM3_B;
c->C = SM3_C;
c->D = SM3_D;
c->E = SM3_E;
c->F = SM3_F;
c->G = SM3_G;
c->H = SM3_H;
return 1;
}
void ossl_sm3_block_data_order(SM3_CTX *ctx, const void *p, size_t num)
{
const unsigned char *data = p;
register unsigned MD32_REG_T A, B, C, D, E, F, G, H;
unsigned MD32_REG_T W00, W01, W02, W03, W04, W05, W06, W07,
W08, W09, W10, W11, W12, W13, W14, W15;
for (; num--;) {
A = ctx->A;
B = ctx->B;
C = ctx->C;
D = ctx->D;
E = ctx->E;
F = ctx->F;
G = ctx->G;
H = ctx->H;
/*
* We have to load all message bytes immediately since SM3 reads
* them slightly out of order.
*/
(void)HOST_c2l(data, W00);
(void)HOST_c2l(data, W01);
(void)HOST_c2l(data, W02);
(void)HOST_c2l(data, W03);
(void)HOST_c2l(data, W04);
(void)HOST_c2l(data, W05);
(void)HOST_c2l(data, W06);
(void)HOST_c2l(data, W07);
(void)HOST_c2l(data, W08);
(void)HOST_c2l(data, W09);
(void)HOST_c2l(data, W10);
(void)HOST_c2l(data, W11);
(void)HOST_c2l(data, W12);
(void)HOST_c2l(data, W13);
(void)HOST_c2l(data, W14);
(void)HOST_c2l(data, W15);
R1(A, B, C, D, E, F, G, H, 0x79CC4519, W00, W00 ^ W04);
W00 = EXPAND(W00, W07, W13, W03, W10);
R1(D, A, B, C, H, E, F, G, 0xF3988A32, W01, W01 ^ W05);
W01 = EXPAND(W01, W08, W14, W04, W11);
R1(C, D, A, B, G, H, E, F, 0xE7311465, W02, W02 ^ W06);
W02 = EXPAND(W02, W09, W15, W05, W12);
R1(B, C, D, A, F, G, H, E, 0xCE6228CB, W03, W03 ^ W07);
W03 = EXPAND(W03, W10, W00, W06, W13);
R1(A, B, C, D, E, F, G, H, 0x9CC45197, W04, W04 ^ W08);
W04 = EXPAND(W04, W11, W01, W07, W14);
R1(D, A, B, C, H, E, F, G, 0x3988A32F, W05, W05 ^ W09);
W05 = EXPAND(W05, W12, W02, W08, W15);
R1(C, D, A, B, G, H, E, F, 0x7311465E, W06, W06 ^ W10);
W06 = EXPAND(W06, W13, W03, W09, W00);
R1(B, C, D, A, F, G, H, E, 0xE6228CBC, W07, W07 ^ W11);
W07 = EXPAND(W07, W14, W04, W10, W01);
R1(A, B, C, D, E, F, G, H, 0xCC451979, W08, W08 ^ W12);
W08 = EXPAND(W08, W15, W05, W11, W02);
R1(D, A, B, C, H, E, F, G, 0x988A32F3, W09, W09 ^ W13);
W09 = EXPAND(W09, W00, W06, W12, W03);
R1(C, D, A, B, G, H, E, F, 0x311465E7, W10, W10 ^ W14);
W10 = EXPAND(W10, W01, W07, W13, W04);
R1(B, C, D, A, F, G, H, E, 0x6228CBCE, W11, W11 ^ W15);
W11 = EXPAND(W11, W02, W08, W14, W05);
R1(A, B, C, D, E, F, G, H, 0xC451979C, W12, W12 ^ W00);
W12 = EXPAND(W12, W03, W09, W15, W06);
R1(D, A, B, C, H, E, F, G, 0x88A32F39, W13, W13 ^ W01);
W13 = EXPAND(W13, W04, W10, W00, W07);
R1(C, D, A, B, G, H, E, F, 0x11465E73, W14, W14 ^ W02);
W14 = EXPAND(W14, W05, W11, W01, W08);
R1(B, C, D, A, F, G, H, E, 0x228CBCE6, W15, W15 ^ W03);
W15 = EXPAND(W15, W06, W12, W02, W09);
R2(A, B, C, D, E, F, G, H, 0x9D8A7A87, W00, W00 ^ W04);
W00 = EXPAND(W00, W07, W13, W03, W10);
R2(D, A, B, C, H, E, F, G, 0x3B14F50F, W01, W01 ^ W05);
W01 = EXPAND(W01, W08, W14, W04, W11);
R2(C, D, A, B, G, H, E, F, 0x7629EA1E, W02, W02 ^ W06);
W02 = EXPAND(W02, W09, W15, W05, W12);
R2(B, C, D, A, F, G, H, E, 0xEC53D43C, W03, W03 ^ W07);
W03 = EXPAND(W03, W10, W00, W06, W13);
R2(A, B, C, D, E, F, G, H, 0xD8A7A879, W04, W04 ^ W08);
W04 = EXPAND(W04, W11, W01, W07, W14);
R2(D, A, B, C, H, E, F, G, 0xB14F50F3, W05, W05 ^ W09);
W05 = EXPAND(W05, W12, W02, W08, W15);
R2(C, D, A, B, G, H, E, F, 0x629EA1E7, W06, W06 ^ W10);
W06 = EXPAND(W06, W13, W03, W09, W00);
R2(B, C, D, A, F, G, H, E, 0xC53D43CE, W07, W07 ^ W11);
W07 = EXPAND(W07, W14, W04, W10, W01);
R2(A, B, C, D, E, F, G, H, 0x8A7A879D, W08, W08 ^ W12);
W08 = EXPAND(W08, W15, W05, W11, W02);
R2(D, A, B, C, H, E, F, G, 0x14F50F3B, W09, W09 ^ W13);
W09 = EXPAND(W09, W00, W06, W12, W03);
R2(C, D, A, B, G, H, E, F, 0x29EA1E76, W10, W10 ^ W14);
W10 = EXPAND(W10, W01, W07, W13, W04);
R2(B, C, D, A, F, G, H, E, 0x53D43CEC, W11, W11 ^ W15);
W11 = EXPAND(W11, W02, W08, W14, W05);
R2(A, B, C, D, E, F, G, H, 0xA7A879D8, W12, W12 ^ W00);
W12 = EXPAND(W12, W03, W09, W15, W06);
R2(D, A, B, C, H, E, F, G, 0x4F50F3B1, W13, W13 ^ W01);
W13 = EXPAND(W13, W04, W10, W00, W07);
R2(C, D, A, B, G, H, E, F, 0x9EA1E762, W14, W14 ^ W02);
W14 = EXPAND(W14, W05, W11, W01, W08);
R2(B, C, D, A, F, G, H, E, 0x3D43CEC5, W15, W15 ^ W03);
W15 = EXPAND(W15, W06, W12, W02, W09);
R2(A, B, C, D, E, F, G, H, 0x7A879D8A, W00, W00 ^ W04);
W00 = EXPAND(W00, W07, W13, W03, W10);
R2(D, A, B, C, H, E, F, G, 0xF50F3B14, W01, W01 ^ W05);
W01 = EXPAND(W01, W08, W14, W04, W11);
R2(C, D, A, B, G, H, E, F, 0xEA1E7629, W02, W02 ^ W06);
W02 = EXPAND(W02, W09, W15, W05, W12);
R2(B, C, D, A, F, G, H, E, 0xD43CEC53, W03, W03 ^ W07);
W03 = EXPAND(W03, W10, W00, W06, W13);
R2(A, B, C, D, E, F, G, H, 0xA879D8A7, W04, W04 ^ W08);
W04 = EXPAND(W04, W11, W01, W07, W14);
R2(D, A, B, C, H, E, F, G, 0x50F3B14F, W05, W05 ^ W09);
W05 = EXPAND(W05, W12, W02, W08, W15);
R2(C, D, A, B, G, H, E, F, 0xA1E7629E, W06, W06 ^ W10);
W06 = EXPAND(W06, W13, W03, W09, W00);
R2(B, C, D, A, F, G, H, E, 0x43CEC53D, W07, W07 ^ W11);
W07 = EXPAND(W07, W14, W04, W10, W01);
R2(A, B, C, D, E, F, G, H, 0x879D8A7A, W08, W08 ^ W12);
W08 = EXPAND(W08, W15, W05, W11, W02);
R2(D, A, B, C, H, E, F, G, 0x0F3B14F5, W09, W09 ^ W13);
W09 = EXPAND(W09, W00, W06, W12, W03);
R2(C, D, A, B, G, H, E, F, 0x1E7629EA, W10, W10 ^ W14);
W10 = EXPAND(W10, W01, W07, W13, W04);
R2(B, C, D, A, F, G, H, E, 0x3CEC53D4, W11, W11 ^ W15);
W11 = EXPAND(W11, W02, W08, W14, W05);
R2(A, B, C, D, E, F, G, H, 0x79D8A7A8, W12, W12 ^ W00);
W12 = EXPAND(W12, W03, W09, W15, W06);
R2(D, A, B, C, H, E, F, G, 0xF3B14F50, W13, W13 ^ W01);
W13 = EXPAND(W13, W04, W10, W00, W07);
R2(C, D, A, B, G, H, E, F, 0xE7629EA1, W14, W14 ^ W02);
W14 = EXPAND(W14, W05, W11, W01, W08);
R2(B, C, D, A, F, G, H, E, 0xCEC53D43, W15, W15 ^ W03);
W15 = EXPAND(W15, W06, W12, W02, W09);
R2(A, B, C, D, E, F, G, H, 0x9D8A7A87, W00, W00 ^ W04);
W00 = EXPAND(W00, W07, W13, W03, W10);
R2(D, A, B, C, H, E, F, G, 0x3B14F50F, W01, W01 ^ W05);
W01 = EXPAND(W01, W08, W14, W04, W11);
R2(C, D, A, B, G, H, E, F, 0x7629EA1E, W02, W02 ^ W06);
W02 = EXPAND(W02, W09, W15, W05, W12);
R2(B, C, D, A, F, G, H, E, 0xEC53D43C, W03, W03 ^ W07);
W03 = EXPAND(W03, W10, W00, W06, W13);
R2(A, B, C, D, E, F, G, H, 0xD8A7A879, W04, W04 ^ W08);
R2(D, A, B, C, H, E, F, G, 0xB14F50F3, W05, W05 ^ W09);
R2(C, D, A, B, G, H, E, F, 0x629EA1E7, W06, W06 ^ W10);
R2(B, C, D, A, F, G, H, E, 0xC53D43CE, W07, W07 ^ W11);
R2(A, B, C, D, E, F, G, H, 0x8A7A879D, W08, W08 ^ W12);
R2(D, A, B, C, H, E, F, G, 0x14F50F3B, W09, W09 ^ W13);
R2(C, D, A, B, G, H, E, F, 0x29EA1E76, W10, W10 ^ W14);
R2(B, C, D, A, F, G, H, E, 0x53D43CEC, W11, W11 ^ W15);
R2(A, B, C, D, E, F, G, H, 0xA7A879D8, W12, W12 ^ W00);
R2(D, A, B, C, H, E, F, G, 0x4F50F3B1, W13, W13 ^ W01);
R2(C, D, A, B, G, H, E, F, 0x9EA1E762, W14, W14 ^ W02);
R2(B, C, D, A, F, G, H, E, 0x3D43CEC5, W15, W15 ^ W03);
ctx->A ^= A;
ctx->B ^= B;
ctx->C ^= C;
ctx->D ^= D;
ctx->E ^= E;
ctx->F ^= F;
ctx->G ^= G;
ctx->H ^= H;
}
}

119
openssl-3.4.2/crypto/sm3/sm3_local.h Normal file
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@@ -0,0 +1,119 @@
/*
* Copyright 2017-2024 The OpenSSL Project Authors. All Rights Reserved.
* Copyright 2017 Ribose Inc. All Rights Reserved.
* Ported from Ribose contributions from Botan.
*
* Licensed under the Apache License 2.0 (the "License"). You may not use
* this file except in compliance with the License. You can obtain a copy
* in the file LICENSE in the source distribution or at
* https://www.openssl.org/source/license.html
*/
#include <string.h>
#include "internal/sm3.h"
#define DATA_ORDER_IS_BIG_ENDIAN
#define HASH_LONG SM3_WORD
#define HASH_CTX SM3_CTX
#define HASH_CBLOCK SM3_CBLOCK
#define HASH_UPDATE ossl_sm3_update
#define HASH_TRANSFORM ossl_sm3_transform
#define HASH_FINAL ossl_sm3_final
#define HASH_MAKE_STRING(c, s) \
do { \
unsigned long ll; \
ll=(c)->A; (void)HOST_l2c(ll, (s)); \
ll=(c)->B; (void)HOST_l2c(ll, (s)); \
ll=(c)->C; (void)HOST_l2c(ll, (s)); \
ll=(c)->D; (void)HOST_l2c(ll, (s)); \
ll=(c)->E; (void)HOST_l2c(ll, (s)); \
ll=(c)->F; (void)HOST_l2c(ll, (s)); \
ll=(c)->G; (void)HOST_l2c(ll, (s)); \
ll=(c)->H; (void)HOST_l2c(ll, (s)); \
} while (0)
#if defined(OPENSSL_SM3_ASM)
# if defined(__aarch64__) || defined(_M_ARM64)
# include "crypto/arm_arch.h"
# define HWSM3_CAPABLE (OPENSSL_armcap_P & ARMV8_SM3)
void ossl_hwsm3_block_data_order(SM3_CTX *c, const void *p, size_t num);
# endif
# if defined(OPENSSL_CPUID_OBJ) && defined(__riscv) && __riscv_xlen == 64
# include "crypto/riscv_arch.h"
# define HWSM3_CAPABLE 1
void ossl_hwsm3_block_data_order(SM3_CTX *c, const void *p, size_t num);
# endif
#endif
#if defined(HWSM3_CAPABLE)
# define HASH_BLOCK_DATA_ORDER (HWSM3_CAPABLE ? ossl_hwsm3_block_data_order \
: ossl_sm3_block_data_order)
#else
# define HASH_BLOCK_DATA_ORDER ossl_sm3_block_data_order
#endif
void ossl_sm3_block_data_order(SM3_CTX *c, const void *p, size_t num);
void ossl_sm3_transform(SM3_CTX *c, const unsigned char *data);
#include "crypto/md32_common.h"
#ifndef PEDANTIC
# if defined(__GNUC__) && __GNUC__>=2 && \
!defined(OPENSSL_NO_ASM) && !defined(OPENSSL_NO_INLINE_ASM)
# if defined(__riscv_zksh)
# define P0(x) ({ MD32_REG_T ret; \
asm ("sm3p0 %0, %1" \
: "=r"(ret) \
: "r"(x)); ret; })
# define P1(x) ({ MD32_REG_T ret; \
asm ("sm3p1 %0, %1" \
: "=r"(ret) \
: "r"(x)); ret; })
# endif
# endif
#endif
#ifndef P0
# define P0(X) (X ^ ROTATE(X, 9) ^ ROTATE(X, 17))
#endif
#ifndef P1
# define P1(X) (X ^ ROTATE(X, 15) ^ ROTATE(X, 23))
#endif
#define FF0(X,Y,Z) (X ^ Y ^ Z)
#define GG0(X,Y,Z) (X ^ Y ^ Z)
#define FF1(X,Y,Z) ((X & Y) | ((X | Y) & Z))
#define GG1(X,Y,Z) ((Z ^ (X & (Y ^ Z))))
#define EXPAND(W0,W7,W13,W3,W10) \
(P1(W0 ^ W7 ^ ROTATE(W13, 15)) ^ ROTATE(W3, 7) ^ W10)
#define RND(A, B, C, D, E, F, G, H, TJ, Wi, Wj, FF, GG) \
do { \
const SM3_WORD A12 = ROTATE(A, 12); \
const SM3_WORD A12_SM = A12 + E + TJ; \
const SM3_WORD SS1 = ROTATE(A12_SM, 7); \
const SM3_WORD TT1 = FF(A, B, C) + D + (SS1 ^ A12) + (Wj); \
const SM3_WORD TT2 = GG(E, F, G) + H + SS1 + Wi; \
B = ROTATE(B, 9); \
D = TT1; \
F = ROTATE(F, 19); \
H = P0(TT2); \
} while(0)
#define R1(A,B,C,D,E,F,G,H,TJ,Wi,Wj) \
RND(A,B,C,D,E,F,G,H,TJ,Wi,Wj,FF0,GG0)
#define R2(A,B,C,D,E,F,G,H,TJ,Wi,Wj) \
RND(A,B,C,D,E,F,G,H,TJ,Wi,Wj,FF1,GG1)
#define SM3_A 0x7380166fUL
#define SM3_B 0x4914b2b9UL
#define SM3_C 0x172442d7UL
#define SM3_D 0xda8a0600UL
#define SM3_E 0xa96f30bcUL
#define SM3_F 0x163138aaUL
#define SM3_G 0xe38dee4dUL
#define SM3_H 0xb0fb0e4eUL

29
openssl-3.4.2/crypto/sm3/sm3_riscv.c Normal file
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@@ -0,0 +1,29 @@
/*
* Copyright 2023 The OpenSSL Project Authors. All Rights Reserved.
*
* Licensed under the Apache License 2.0 (the "License"). You may not use
* this file except in compliance with the License. You can obtain a copy
* in the file LICENSE in the source distribution or at
* https://www.openssl.org/source/license.html
*/
#include <stdlib.h>
#include <string.h>
#include <openssl/opensslconf.h>
#include "internal/sm3.h"
#include "crypto/riscv_arch.h"
#include <stdio.h>
void ossl_hwsm3_block_data_order_zvksh(SM3_CTX *c, const void *p, size_t num);
void ossl_sm3_block_data_order(SM3_CTX *c, const void *p, size_t num);
void ossl_hwsm3_block_data_order(SM3_CTX *c, const void *p, size_t num);
void ossl_hwsm3_block_data_order(SM3_CTX *c, const void *p, size_t num)
{
if (RISCV_HAS_ZVKB_AND_ZVKSH() && riscv_vlen() >= 128) {
ossl_hwsm3_block_data_order_zvksh(c, p, num);
} else {
ossl_sm3_block_data_order(c, p, num);
}
}